Intelligent Memory IM5116SDBBBG-6I SDRAM 512 MB Surface, 54-Pin 16 bit FBGA
- RS Stock No.:
- 588-656
- Mfr. Part No.:
- IM5116SDBBBG-6I
- Manufacturer:
- Intelligent Memory
Subtotal (1 unit)*
SGD17.03
(exc. GST)
SGD18.56
(inc. GST)
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Units | Per unit |
|---|---|
| 1 + | SGD17.03 |
*price indicative
- RS Stock No.:
- 588-656
- Mfr. Part No.:
- IM5116SDBBBG-6I
- Manufacturer:
- Intelligent Memory
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Intelligent Memory | |
| Product Type | SDRAM | |
| Memory Size | 512MB | |
| Organisation | 32M x 16 | |
| Data Bus Width | 16bit | |
| Address Bus Width | 13bit | |
| Maximum Clock Frequency | 166MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 6ns | |
| Number of Words | 33554432 Words | |
| Mount Type | Surface | |
| Package Type | FBGA | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 54 | |
| Maximum Operating Temperature | 85°C | |
| Length | 8mm | |
| Standards/Approvals | RoHS | |
| Width | 8 mm | |
| Height | 1.2mm | |
| Series | IM5116SDBB | |
| Supply Current | 140mA | |
| Maximum Supply Voltage | 3.6V | |
| Automotive Standard | AEC-Q100 | |
| Minimum Supply Voltage | 3V | |
| Select all | ||
|---|---|---|
Brand Intelligent Memory | ||
Product Type SDRAM | ||
Memory Size 512MB | ||
Organisation 32M x 16 | ||
Data Bus Width 16bit | ||
Address Bus Width 13bit | ||
Maximum Clock Frequency 166MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 6ns | ||
Number of Words 33554432 Words | ||
Mount Type Surface | ||
Package Type FBGA | ||
Minimum Operating Temperature -40°C | ||
Pin Count 54 | ||
Maximum Operating Temperature 85°C | ||
Length 8mm | ||
Standards/Approvals RoHS | ||
Width 8 mm | ||
Height 1.2mm | ||
Series IM5116SDBB | ||
Supply Current 140mA | ||
Maximum Supply Voltage 3.6V | ||
Automotive Standard AEC-Q100 | ||
Minimum Supply Voltage 3V | ||
The Intelligent Memory Four bank Synchronous DRAM is organized as 4 banks x 8Mbit x 16. It achieves high-speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and synchronizes the output data to the system clock. All control, address, data input, and output circuits are synchronized with the positive edge of an externally supplied clock to ensure precise timing and reliable performance.
Power down mode
Auto refresh and self refresh
Automatic and controlled precharge command
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