Nexperia 8-Bit Octal D Type Latch, Transparent, 3 State, 20-Pin TSSOP
- RS Stock No.:
- 170-5424P
- Mfr. Part No.:
- 74LVC573APW,118
- Manufacturer:
- Nexperia
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Subtotal 125 units (supplied on a continuous strip)*
SGD35.50
(exc. GST)
SGD38.75
(inc. GST)
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- Shipping from 10 August 2026
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Units | Per unit |
|---|---|
| 125 - 225 | SGD0.284 |
| 250 - 725 | SGD0.276 |
| 750 - 1475 | SGD0.267 |
| 1500 + | SGD0.259 |
*price indicative
- RS Stock No.:
- 170-5424P
- Mfr. Part No.:
- 74LVC573APW,118
- Manufacturer:
- Nexperia
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Logic Family | 74LVC | |
| Product Type | Octal D Type Latch | |
| Logic Function | D Type | |
| Latch Mode | Transparent | |
| Number of Bits | 8 | |
| Number of Channels | 8 | |
| Output Type | 3 State | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 1.2V | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Standards/Approvals | No | |
| Length | 6.6mm | |
| Series | 74LVC | |
| Width | 4.5 mm | |
| Height | 0.95mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Logic Family 74LVC | ||
Product Type Octal D Type Latch | ||
Logic Function D Type | ||
Latch Mode Transparent | ||
Number of Bits 8 | ||
Number of Channels 8 | ||
Output Type 3 State | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Minimum Supply Voltage 1.2V | ||
Package Type TSSOP | ||
Pin Count 20 | ||
Maximum Supply Voltage 3.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Standards/Approvals No | ||
Length 6.6mm | ||
Series 74LVC | ||
Width 4.5 mm | ||
Height 0.95mm | ||
Automotive Standard No | ||
- COO (Country of Origin):
- CN
The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all internal latches. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, that is, a latch output will change each time its corresponding D-input changes.
Mixed 5 V and 3.3 V applications
Save board space
Low cost Interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Memory controllers
Backplane interfaces
Related links
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