83026BGI-01LF, Clock Buffer, 1-Input, 8-Pin SOIC
- RS Stock No.:
- 216-6199
- Mfr. Part No.:
- 83026BGI-01LF
- Manufacturer:
- Renesas Electronics
Bulk discount available
Subtotal (1 pack of 2 units)*
SGD17.37
(exc. GST)
SGD18.934
(inc. GST)
FREE delivery for orders over $150, or create a business account to enjoy free delivery from just $28
In Stock
- Plus 410 unit(s) shipping from 05 January 2026
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Units | Per unit | Per Pack* |
|---|---|---|
| 2 - 8 | SGD8.685 | SGD17.37 |
| 10 - 18 | SGD8.425 | SGD16.85 |
| 20 - 48 | SGD8.09 | SGD16.18 |
| 50 - 98 | SGD7.685 | SGD15.37 |
| 100 + | SGD7.22 | SGD14.44 |
*price indicative
- RS Stock No.:
- 216-6199
- Mfr. Part No.:
- 83026BGI-01LF
- Manufacturer:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Logic Function | Clock Buffer | |
| Number of Clock Inputs | 1 | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Logic Function Clock Buffer | ||
Number of Clock Inputs 1 | ||
Package Type SOIC | ||
Pin Count 8 | ||
The Renesas Electronics 83026I-01 is a low skew, 1-to-2 Differential-to-LVCMOS/ LVTTL Fanout Buffer. The differential input can accept most differential signal types (LVPECL, LVDS, LVHSTL, HCSL and SSTL) and translate to two single-ended LVCMOS/LVTTL outputs. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space.
Two LVCMOS / LVTTL outputs
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 350MHz
Output skew: 15ps (maximum)
Part-to-part skew: 600ps (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
Small 8 lead SOIC package saves board space
3.3V core, 3.3V, 2.5V or 1.8V output operating supply
-40°C to 85°C ambient operating temperature
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 350MHz
Output skew: 15ps (maximum)
Part-to-part skew: 600ps (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
Small 8 lead SOIC package saves board space
3.3V core, 3.3V, 2.5V or 1.8V output operating supply
-40°C to 85°C ambient operating temperature