- RS Stock No.:
- 188-2835
- Mfr. Part No.:
- W972GG6KB25I
- Manufacturer:
- Winbond
16 In stock for delivery within 4 working days
Added
Price Each
SGD18.44
(exc. GST)
SGD20.10
(inc. GST)
Units | Per unit |
1 - 9 | SGD18.44 |
10 - 24 | SGD17.07 |
25 - 49 | SGD16.68 |
50 - 99 | SGD16.59 |
100 + | SGD14.62 |
- RS Stock No.:
- 188-2835
- Mfr. Part No.:
- W972GG6KB25I
- Manufacturer:
- Winbond
Technical data sheets
Legislation and Compliance
Product Details
The W972GG6KB is a 2G bits DDR2 SDRAM, and speed involving -18, -25/25I, and -3/-3I.
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and /CLK)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
Posted /CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and /CLK)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
Posted /CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
For products that are Customized and under Non-cancellable & Non-returnable, Sales & Conditions apply.
Specifications
Attribute | Value |
---|---|
Memory Size | 2Gbit |
Organisation | 256M x 8 bit |
SDRAM Class | DDR2 |
Data Rate | 800MHz |
Data Bus Width | 16bit |
Address Bus Width | 17bit |
Number of Bits per Word | 8bit |
Maximum Random Access Time | 0.4ns |
Number of Words | 256M |
Mounting Type | Surface Mount |
Package Type | WBGA |
Pin Count | 84 |
Dimensions | 12.6 x 8.1 x 0.6mm |
Height | 0.6mm |
Length | 12.6mm |
Minimum Operating Supply Voltage | 1.7 V |
Minimum Operating Temperature | -40 °C |
Maximum Operating Temperature | +95 °C |
Width | 8.1mm |
Maximum Operating Supply Voltage | 1.9 V |