Cypress Semiconductor, CY2304SXC-1

Technical data sheets
Legislation and Compliance
RoHS Certificate of Compliance
Product Details

The CY2304 is a 3.3 V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps. The CY2304 has two banks of two outputs each. The CY2304 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 μA of current draw. Multiple CY2304 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500 ps. The CY2304 is available in two different configurations.

Specifications
Attribute Value
Number of Elements per Chip 1
Maximum Supply Current 45 mA
Maximum Input Frequency 133MHz
Mounting Type Surface Mount
Package Type SOIC
Pin Count 8
Dimensions 4.97 x 3.98 x 1.47mm
Length 4.97mm
Width 3.98mm
Height 1.47mm
Maximum Operating Supply Voltage 3.6 V
Maximum Operating Temperature +70 °C
Maximum Output Frequency 133.3MHz
Minimum Operating Supply Voltage 3 V
Minimum Output Frequency 10MHz
Minimum Operating Temperature 0 °C
97 In stock for delivery within 4 working days
Price Each (In a Tube of 97)
SGD 9.741
(exc. GST)
SGD 10.423
(inc. GST)
units
Per unit
Per Tube*
97 - 97
SGD9.741
SGD944.877
194 - 194
SGD9.369
SGD908.793
291 - 485
SGD8.866
SGD860.002
582 - 970
SGD8.078
SGD783.566
1067 +
SGD7.674
SGD744.378
*price indicative
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